Semiconductor device featuring common capacitor electrode layer, and method for manufacturing such semiconductor device

Abstract

In a semiconductor device, a semiconductor substrate is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed. A multi-layered insulating layer is formed on the substrate, and a conductive structure is formed in the insulating layer at the logic-circuit formation section. Capacitors are formed in the insulating layer at the memory formation section. Each of the capacitors includes a lower capacitor electrode, a capacitor dielectric layer formed on the lower capacitor electrode, and an upper capacitor electrode formed on the capacitor dielectric layer, with upper is end faces of the upper capacitor electrodes being coplanar with an upper end face of the conductive structure. Bit-line layers are formed in the insulating layer below the lower capacitor electrodes at the memory formation section. A signal-line layer is formed in the insulating layer on or above the conductive structure at the logic-circuit formation section so as to be electrically connected to the conductive structure. An upper-side connection layer are formed in the insulating layer at the memory formation section on or above the capacitors so as to be electrically connected to the upper capacitor electrodes.

Claims

1 . A semiconductor device comprising: a semiconductor substrate which is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed; a multi-layered insulating layer formed on said semiconductor substrate; a conductive structure formed in said multi-layered insulating layer at said logic-circuit formation section; a plurality of capacitors formed in said multi-layered insulating layer at said memory formation section, each of said capacitors including a lower capacitor electrode, a capacitor dielectric layer formed on said lower capacitor electrode, and an upper capacitor electrode formed on said capacitor dielectric layer, upper faces of said upper capacitor electrodes being coplanar with an upper face of said conductive structure; a plurality of lower-side connection layers formed in said multi-layered insulating layer below the lower capacitor electrodes of said capacitors at said memory formation section; a logic-circuit-side connection layer formed in said multi-layered insulating layer on or above said conductive structure at said logic-circuit formation section so as to be electrically connected to said conductive structure; and an upper-side connection layer formed in said multi-layered insulating layer at the memory formation section on or above said capacitors so as to be electrically connected to the upper capacitor electrodes of said capacitors. 2 . The semiconductor device as set forth in claim 1 , wherein an uppermost portion of each of the upper capacitor electrodes is formed as a capacitor conductive plug with which an upper face of the corresponding capacitor dielectric layer is covered. 3 . The semiconductor device as set forth in claim 1 , wherein said conductive structure is formed as a contact structure. 4 . The semiconductor device as set forth in claim 3 , wherein a height of said contact structure is equivalent, to a height of said capacitors. 5 . The semiconductor device as set forth in claim 1 , wherein said conductive structure comprises a first signal-line layer having a via plug formed thereon, and a second signal-line layer positioned above said first signal-line layer and electrically connected to said via plug. 6 . The semiconductor device as set forth in claim 5 , wherein a total height of said first and second signal-line layer and said via plug is equivalent to a height of said capacitors. 7 . The semiconductor device as set forth in claim 1 , wherein each of said lower-side connection layers is formed as a bit-line layer. 8 . The semiconductor device as set forth in claim 1 , wherein said logic-circuit-side connection layer is formed as a signal-line layer, and said upper-side connection layer is formed as a common capacitor electrode layer. 9 . The semiconductor device as set forth in claim 8 , wherein said common capacitor electrode layer is directly and electrically connected to the upper capacitor electrodes of said capacitors. 10 . The semiconductor device as set forth in claim 9 , wherein said common capacitor electrode layer has a lattice-like configuration, and wherein said capacitors are regularly arranged so that an electrical connection is established between said common capacitor electrode layer and the upper capacitor electrodes of said capacitors. 11 . The semiconductor device as set forth in claim 8 , wherein said common capacitor electrode layer has a plurality of via plugs formed on a lower face thereof, and is electrically connected to the upper capacitor electrodes of said capacitors through the intermediary of said respective via plugs. 12 . The semiconductor device as set forth in claim 11 , wherein said common capacitor electrode layer has a lattice-like configuration, and wherein said capacitors are regularly arranged so that an electrical connection is established between said common capacitor electrode layer and is the upper capacitor electrodes of said capacitors. 13 . A method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate which is sectioned into a logic-circuit formation section In which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed; forming a first insulating interlayer on said semiconductor substrate; forming a plurality of lower-side connection layers on said first insulating interlayer at said memory formation section; forming a second insulating interlayer on said first insulating interlayer so that said lower-side connection layers are covered with said second insulating interlayer; forming a first insulating layer on said second insulating interlayer; forming a plurality of openings in said first insulating layer; forming a first conductive layer on said first insulating layer so that inner wall surfaces of said openings are traversed by said first conductive layer; etching back said first conductive layer to thereby define a lower capacitor electrode, derived from said first conductive layer, in each of said openings, so that an upper edge of said lower capacitor electrode is positioned at a predetermined depth measured from an upper peripheral edge of the corresponding opening; forming a dielectric layer on said first insulating layer so that the inner wall surfaces of said openings are traversed by said capacitor dielectric layer; forming a second conductive layer on said capacitor dielectric layer so that said openings are filled with said second conductive layer; removing redundant materials of both said second conductive layer and said dielectric layer from said first insulating layer by using a chemical mechanical polishing process to thereby define a capacitor dielectric layer and an upper capacitor electrode on said lower capacitor electrode in each of said openings, resulting in a formation of a capacitor in the corresponding opening; forming a logic-circuit-side conductive structure in said first insulating layer at said logic-circuit formation section so that upper faces of said upper capacitor electrodes are coplanar with an upper face of said logic-circuit-side conductive structure; forming a second insulating layer on said first insulating layer; and simultaneously forming a logic-circuit-side connection layer and an upper-side connection layer in said second insulating layer at said logic-circuit formation section and said memory formation section, respectively, so that said logic-circuit-side connection layer is electrically connected to said conductive structure, and so that said upper-side connection layer is electrically connected to the upper capacitor electrodes of said capacitors. 14 . The method as set forth in flair 13 , wherein each of said first insulating layer includes at least two insulating interlayers. 15 . The method as set forth in claim 13 , wherein each of said second insulating layer includes at least two insulating interlayers. 16 . A method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate which is sectioned into a logic-circuit formation section in which a is plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed; forming a first insulating interlayer on said semiconductor substrate; forming a plurality of lower-side connection layers on said first insulating interlayer at said memory formation section; forming a second insulating interlayer on said first insulating interlayer so that said lower-side connection layers are covered with said second insulating interlayer; forming a first insulating layer on said second insulating interlayer; forming a plurality of openings in said first insulating layer; forming a first conductive layer on said first insulating layer so that inner wall surfaces of said openings are traversed by said first conductive layer; etching back said first conductive layer to thereby define a lower capacitor electrode, derived from said first conductive layer, in each of said openings, so that an upper edge of said lower capacitor electrode is positioned at a predetermined depth measured from an upper peripheral edge of the corresponding opening; forming a capacitor dielectric layer on said first insulating layer so that the inner wall surfaces of said openings are traversed by said capacitor dielectric layer; forming a second conductive layer on said capacitor dielectric layer so that said openings are filled with said second conductive layer; etching back both said second conductive layer and said insulating layer so that redundant materials of both said second conductive layer and said insulating layer are removed from said first insulating layer, and so that respective recesses are defined at locations of said openings, to thereby define a capacitor dielectric layer and an upper capacitor electrode on said lower capacitor electrode in each of said openings, resulting in a formation of a capacitor in the corresponding opening; forming a logic-circuit-side conductive structure in said first insulating layer at said logic-circuit formation section, simultaneously forming capacitor conductive plugs in said recesses, so that upper faces of said capacitor conductive plugs are coplanar with an upper face of said logic-circuit-side conductive structure; forming a second insulating layer on said first insulating layer; and simultaneously forming a logic-circuit-side connection layer and an upper-side connection layer in said second insulating layer at said logic-circuit formation section and said memory formation section, respectively, so that said logic-circuit-side connection layer is electrically connected to said conductive structure, and so that said upper-side connection layer is electrically connected to said capacitor conductive plugs. 17 . The method as set forth in claim 16 , wherein each of said first insulating layer includes at least two Insulating interlayers. 18 . The method as set forth in claim 16 , wherein each of said second insulating layer includes at least two insulating interlayers.
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device including a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed, and relates to a method for manufacturing such a semiconductor device. [0003] 2. Description of the Related Art [0004] For example, as disclosed in JP-2004-235246 A and JP-2005-005337 A, a prior art semiconductor device, which is called a large scale integrated (LSI) circuit, may include a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed. When the semiconductor device needs a large capacity memory, such a memory is formed as a dynamic random access memory (DRAM) in the memory formation section because memory cells of the DRAM can be formed in the memory formation section in a relatively small area. SUMMARY OF THE INVENTION [0005] It has now been discovered that the above-mentioned prior art semiconductor device has a problem to be solved as mentioned hereinbelow. [0006] In the prior art semiconductor device, both the logic-circuit formation section and the memory formation section are simultaneously constructed in a semiconductor substrate such as a silicon substrate by using a well-known variety of processes such as a photolithography process, an etching process, a chemical vapor deposition (CVD) process, a sputtering process, a chemical mechanical polishing (CMP) process and so on. [0007] In this case, it is necessary to contrive an arrangement of the semiconductor device so that the construction of the logic-circuit formation section and the construction of the memory formation section cannot exert a negative influence on each other, and so that the constructions can be efficiently carried out, as will be discussed in detail hereinafter. [0008] In accordance with a first aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate which is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed. A multi-layered insulating layer is formed on the semiconductor substrate, and a conductive structure is formed in the multi-layered insulating layer at the logic-circuit formation section. A plurality of capacitors are formed in the multi-layered insulating layer at the memory formation section, and each of the capacitors includes a lower capacitor electrode, a capacitor dielectric layer formed on the lower capacitor electrode, and an upper capacitor electrode formed on the capacitor dielectric layer, with upper faces of the upper capacitor electrodes being coplanar with an upper face of the conductive structure. A plurality of lower-side connection layers are formed in the multi-layered insulating layer below the lower capacitor electrodes of the capacitors at the memory formation section, and a logic-circuit-side connection layer is formed in the multi-layered insulating layer on or above the conductive structure at the logic-circuit formation section so as to be electrically connected to the conductive structure. An upper-side connection layer is formed in the multi-layered insulating layer at the memory formation section on or above the capacitors so as to be electrically connected to the upper capacitor electrodes of the capacitors. [0009] An uppermost portion of each of the upper capacitor electrodes may be formed as a capacitor conductive plug, with which an upper face of the corresponding capacitor dielectric layer is covered. [0010] The conductive structure may be formed as a contact structure. In this case, a height of the contact structure is equivalent to the height of the capacitors. [0011] Also, the conductive structure may include a first signal-line layer having a via plug formed thereon, and a is second signal-line layer positioned above the first signal-line layer and electrically connected to the via plug. [0012] In this case, a total height of the first and second signal-line layer and the via plug is equivalent to the height of the capacitors. Each of the lower-side connection layers may be formed as a bit-line layer. [0013] The logic-circuit-side connection layer may be formed as a signal-line layer, and the upper-side connection layer may be formed as a common capacitor electrode layer. In this case, the common capacitor electrode layer may be directly and electrically connected to the upper capacitor electrodes of the capacitors. In this case, preferably, the common capacitor electrode layer has a lattice-like configuration, and the capacitors are regularly arranged so that an electrical connection is established between the common capacitor electrode layer and the upper capacitor electrodes of the capacitors. [0014] The common capacitor electrode layer may have a plurality of via plugs formed on a lower face thereof. In this case, the common capacitor electrode layer is electrically connected to the upper capacitor electrodes of the capacitors through the intermediary of the respective via plugs. In this case, the common capacitor electrode layer may have a lattice-like configuration, and the capacitors are regularly arranged so that an electrical connection is established between the common capacitor electrode layer and the upper capacitor electrodes of the capacitors. [0015] In accordance with a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate which is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed; forming a first insulating interlayer on the semiconductor substrate; forming a plurality of lower-side connection layers on the first insulating interlayer at the memory formation section; forming a second insulating interlayer on the first insulating interlayer so that the lower-side connection layers are covered with the second insulating interlayer; forming a first insulating layer on the second insulating interlayer; forming a plurality of openings in the first insulating layer; forming a first conductive layer on the first insulating layer so that inner wall surfaces of the openings are traversed by the first conductive layer; etching back the first conductive layer to thereby define a lower capacitor electrode, derived from the first conductive layer, in each of the openings, so that an upper edge of the lower capacitor electrode is positioned at a predetermined depth measured from an upper peripheral edge of the corresponding opening; forming a dielectric layer on the first insulating layer so that the inner wall surfaces of the openings are traversed by the capacitor dielectric layer; forming a second conductive layer on the capacitor dielectric layer so that the openings are filled with the second conductive layer; removing redundant materials of both the second conductive layer and the dielectric layer from the first insulating layer by using a chemical mechanical polishing (CHP) process to thereby define a capacitor dielectric layer and an upper capacitor electrode on the lower capacitor electrode in each of the openings, resulting in a formation of a capacitor in the corresponding opening; forming a logic-circuit-side conductive structure in the first insulating layer at the logic-circuit formation section so that upper faces of the upper capacitor electrodes are coplanar with an upper face of the logic-circuit-side conductive structure; forming a second insulating layer on the first insulating layer; and simultaneously forming a logic-circuit-side connection layer and an upper-side connection layer in the second insulating layer at the logic-circuit formation section and the memory formation section, respectively, so that the logic-circuit-side connection layer is electrically connected to the conductive structure, and so that the upper-side connection layer is electrically connected to the upper capacitor electrodes of the capacitors. [0016] In accordance with a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate which is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed; forming a first insulating interlayer on the semiconductor substrate; forming a plurality of lower-side connection layers on the first insulating interlayer at the memory formation section; forming a second insulating interlayer on the first insulating interlayer so that the lower-side connection layers are covered with the second insulating interlayer; forming a first insulating layer on the second insulating interlayer; forming a plurality of openings in the first insulating layer; forming a first conductive layer on the first insulating layer so that inner wall surfaces of the openings are traversed by the first conductive layer; etching back the first conductive layer to thereby define a lower capacitor electrode, derived from the first conductive layer, in each of the openings, so that an upper edge of the lower capacitor electrode is positioned at a predetermined depth measured from an upper peripheral edge of the corresponding opening; forming a capacitor dielectric layer is on the first insulating layer so that the inner wall surfaces of the openings are traversed by the capacitor dielectric layer; forming a second conductive layer on the capacitor dielectric layer so that the openings are filled with the second conductive layer; etching back both the second conductive layer and the insulating layer so that redundant materials of both the second conductive layer and the insulating layer are removed from the first insulating layer, and so that respective recesses are defined at locations of the openings, to thereby define a capacitor dielectric layer and an upper capacitor electrode on the lower capacitor electrode in each of the openings, resulting in a formation of a capacitor in the corresponding opening; forming a logic-circuit-side conductive structure in the first insulating layer at the logic-circuit formation section, simultaneously forming capacitor conductive plugs in the recesses, so that upper faces of the capacitor conductive plugs are coplanar with an upper face of the logic-circuit-side conductive structure; forming a second insulating layer on the first insulating layer; and simultaneously forming a logic-circuit-side connection layer and an upper-side connection layer in the second insulating layer at the logic-circuit formation section and the memory formation section, respectively, so that the logic-circuit-side connection layer is electrically connected to the conductive structure, and so that the upper-side connection layer is electrically connected to the capacitor conductive plugs. BRIEF DESCRIPTION OF THE DRAWINGS [0017] The present invention will be more clearly understood from the description set forth below, as compared with the prior art semiconductor device, with reference to the accompanying drawings, wherein: [0018] FIG. 1 is a cross-sectional view of a prior art semiconductor device including a logic-circuit formation section and a memory formation section; [0019] FIGS. 2A to 2P are cross-sectional views for explaining a first embodiment of the method for manufacturing a semiconductor device including a logic-circuit formation section and a memory formation section according to the present invention; [0020] FIG. 3 is a plan view showing a part of the memory formation section of the semiconductor device of FIG. 2P ; [0021] FIGS. 4A to 4G are cross-sectional views for explaining a second embodiment of the method for manufacturing a semiconductor device including a logic-circuit formation section and a memory formation section according to the present invention; [0022] FIG. 5 is a plan view showing a part of the memory formation section of the semiconductor device of FIG. 4G ; [0023] FIGS. 6A to 6I are cross-sectional views for explaining a third embodiment of the method for manufacturing a semiconductor device including a logic-circuit formation section and a memory formation section according to the present invention; and [0024] FIG. 7 is a plan view showing a part of the memory section of the semiconductor device of FIG. 6I . DESCRIPTION OF THE PREFERRED EMBODIMENTS [0025] Before description of embodiments of the present invention, for better understanding of the present invention, with reference to FIG. 1 , a prior art semiconductor device will be explained below. [0026] Referring to FIG. 1 which is a cross-sectional view of a prior art semiconductor device, as disclosed in, for example, JP-2004-356520 A, the prior art semiconductor device is generally indicated by reference numeral 100 , and includes a p-type silicon substrate 101 which is derived from a monocrystalline silicon wafer. [0027] The silicon substrate 101 is sectioned into a logic-circuit formation section 102 L in which a plurality of logic circuits are formed, and a memory formation section 102 M in which a plurality of DRAM cells are formed. [0028] A plurality of element-isolation layers 103 are formed in the silicon substrate 101 by using a shallow-trench isolation (STI) process, so that a plurality of transistor formation areas are defined on the surface of the silicon substrate 101 . In the logic-circuit formation section 102 L, only one of the defined transistor formation areas is representatively indicated by reference 104 L. Also, in the memory formation section 102 M, only three of the defined transistor formation areas are representatively indicated by references 104 M 1 , 104 M 2 and 104 M 3 , respectively. [0029] An n-channel type MOS transistor is formed as a logic transistor in the transistor formation area 104 L, and includes a gate structure 105 L formed on the transistor formation area 104 L, and a pair of source/drain regions 106 L formed in the transistor formation area 104 L. The gate structure 105 L includes a gate insulating layer 105 L 1 , formed on the transistor formation area 104 L, and a gate electrode 105 L 2 formed on the gate insulating layer 105 L 1 . [0030] On the other hand, three n-channel type MOS transistors are respectively formed as DRAM transistors in the transistor formation areas 104 M 1 , 104 M 2 and 104 M 3 , and each of the DRAM transistors includes a gate structure (not shown) formed on the corresponding transistor formation area 104 M 1 , 104 M 2 or 104 M 3 , and a pair of source/drain regions 106 M 1 , 106 M 2 or 106 M 3 formed in the corresponding transistor formation area 104 M 1 , 104 M 2 or 104 M 3 . Similar to the gate structure 105 L, the gate structure (not shown) includes a gate insulating layer on the corresponding transistor formation area 104 M 1 , 104 M 2 or 104 M 3 , and a gate electrode formed on the gate insulating layer. [0031] Note, in FIG. 1 , only one of the source/drain regions 106 M 1 , 106 M 2 or 106 M 3 in each pair is illustrated. [0032] Suitable silicide layers 107 L are formed as interconnect layers on the surface of the silicon substrate 101 at the logic-circuit formation section 102 L so as to be electrically connected to the respective source/drain regions 106 L. [0033] On the other hand, suitable silicide layers 107 M 1 , 107 M 2 and 107 M 3 are formed as interconnect layers on the surface of the silicon substrate 101 at the memory formation section 102 M so as to be electrically connected to the respective source/drain regions 106 M 1 , 106 M 2 and 106 M 3 . [0034] Note, the formation of the silicide layers 107 L and the formation of the silicide layers 107 M 1 , 107 M 2 and 107 M 3 may be simultaneously carried-out by using a so-called salicide process. [0035] A silicon dioxide layer 108 is formed as an insulating interlayer on the surface of the silicon substrate 101 , so that the gate structures 105 L and the silicide layers or interconnect layers 107 L, 107 M 1 , 107 M 2 and 107 M 3 are covered with the insulating interlayer 108 . [0036] A bit-line contact structure 109 is formed in the insulating interlayer 108 by using a photolithography and etching process, a CVD process and so on, so as to be electrically connected to the interconnect layer 107 M 1 . For example, the bit-line contact structure 109 includes a titanium nitride layer 109 1 exhibiting a superior adhesive property to the insulating interlayer or silicon dioxide layer 108 , and a tungsten plug 109 2 exhibiting a superior adhesive property to the titanium nitride layer 109 1 . Note, although the tungsten plug 109 2 exhibits an inferior adhesive property to the silicon dioxide layer 108 , the bit-line contact structure 109 can be securely adhered to the silicon dioxide layer 108 due to the existence of the titanium nitride layer 109 1 . [0037] Connection layers or bit-line layers 110 are formed on the insulating interlayer 108 at the memory formation section 102 M by using a photolithography and etching process, a CVD process and so on, with one of the illustrated bit-line layers 110 being electrically connected to the bit-line contact structure 109 . Each of the bit-line layers 110 includes a tungsten layer 110 1 formed on the insulating interlayer 108 , and a titanium nitride layer 110 2 formed on the tungsten layer 110 1 . [0038] A silicon dioxide layer 111 is formed as an insulating interlayer on the insulating interlayer 108 by using a CVD process, a CMP process and so on, so that the bit-line layers 110 are covered with the insulating interlayer 111 . Note that each of the bit-line layers 110 can be securely adhered to the insulating interlayer 111 due to the titanium nitride layer 110 2 of the bit-line layers 110 . [0039] Logic-circuit-side contact structures 112 L are formed in both the insulating interlayers 108 and 111 at the logic-circuit formation section 102 L so as to be electrically connected to the respective interconnect layers 107 L. For the same reason as in the formation of the bit-line contact structure 109 , each of the logic-circuit-side contact structures 112 L includes a titanium nitride layer 112 L 1 and a tungsten plug 112 L 2 . [0040] On the other hand, memory-side contact structures 112 M are formed in both the insulating interlayers 108 and 111 at the memory formation section 102 M so as to be electrically connected to the respective interconnect layers 107 M 2 and 107 M 3 . Each of the memory-side contact structures 112 M also includes a titanium nitride layer 112 M, and a tungsten plug 112 M 2 . [0041] Note, the formation of the logic-circuit-side contact structures 112 L and the formation of the memory-side contact structures 112 M may be simultaneously carried out by using a photolithography and etching process, a CVD process and so on. [0042] A silicon nitride layer 113 and a silicon dioxide layer 114 are formed in order as insulating interlayers on the insulating interlayer 111 by using a CVD process, a CMP process and so on. Then, a plurality of capacitors 115 are formed in both the insulating interlayers 113 and 114 at the memory formation section 102 M by using a well-known variety of processes such as a photolithography process, an etching process, a CVD process, a CMP process and so on. Note, in FIG. 1 , only two of the capacitors 115 are illustrated by way of example. [0043] In particular, for example, each of the capacitors 115 includes a titanium nitride layer 116 M formed on an inner wall surface of an opening defined in both the insulating interlayers 113 and 114 , a tantalum oxide layer 117 M formed on the titanium nitride layer 116 M, a titanium nitride layer 118 M formed on the tantalum oxide layer 117 M, and a tungsten layer 119 M formed on the titanium nitride layer, with the aforesaid opening being filled with the tungsten layer 119 M. Namely, the titanium nitride layer 116 M serves as a lower capacitor electrode of the capacitor 115 concerned, and the tantalum oxide layer 117 M serves as a capacitor dielectric layer of the capacitor 115 concerned. Also, both the titanium nitride layer 118 M and the tungsten layer 119 M serve as an upper capacitor electrode of the capacitor 115 concerned, [0044] As shown in FIG. 1 , the tantalum oxide layer 117 M is defined as a part of a tantalum oxide layer 117 formed on the insulating interlayer 114 at the memory formation section 102 M. Similarly, the titanium nitride layer 118 M is defined as a part of a titanium nitride layer 118 formed on the tantalum oxide layer 117 , and the tungsten layer 119 M is defined as a part of a tungsten layer 119 formed on the titanium nitride layer 118 , whereby both the titanium nitride layer 118 and the tungsten layer 119 form a common capacitor plate 120 to all the capacitors 115 . Note that the common capacitor plate 120 may be formed by using a photolithography and etching process, an etching process and so on. [0045] A silicon dioxide layer 121 is formed as an insulating interlayer on the insulating interlayer 114 by using a CVD process and a CMP process, so that the common capacitor plate 120 is covered with the insulating interlayer 121 . [0046] Logic-circuit-side contact structures 122 L are formed in both the insulating interlayers 114 and 121 at the logic-circuit formation section 102 L so as to be electrically connected to the respective logic-circuit-side contact structures 112 L. For the same reason as in the formation of the bit-line contact structure 109 , each of the logic contact structures 122 L includes a titanium nitride layer 122 L, and a tungsten plug 122 L. [0047] On the other hand, a memory-side contact structure 122 M is formed in the insulating interlayer 121 at the memory formation section 102 M so as to be electrically connected to the tungsten layer 119 of the common capacitor plate 120 . The memory-side contact structure 122 M also includes a titanium nitride layer 122 M 1 and a tungsten plug 122 M 2 . [0048] A silicon nitride layer 123 and a silicon dioxide layer 124 are formed in order as insulating interlayers on the insulating interlayer 121 by using a CVD process and a CMP process. Signal-line layers 125 L are formed in both the insulating interlayers 123 and 124 so as to be electrically connected to the respective logic-circuit-side contact structures 122 L, and each of the signal-line layers 125 L includes a titanium nitride layer 125 L 1 and a tungsten layer 125 L 2 for the same reason as in the formation of the bit-line contact structure 109 . On the other hand, a memory-side connection layer 125 M, which also includes a titanium nitride layer 125 M 1 and a tungsten layer 125 M 2 , is formed in both the insulating interlayers 123 and 124 so as to be electrically connected to the memory-side contact structure 122 M. [0049] Note that the formation of the signal-line layer 125 L and the formation of the memory-side connection layer 125 M may be simultaneously carried out by using a photolithography and etching process, a CVD process, a CMP process and so on. [0050] Optionally, in each of the signal-line layers 125 L, both a tantalum nitride layer and a tantalum layer may be substituted for the titanium nitride layer 125 L 1 , and a copper layer may be substituted for the tungsten layers 125 L 2 . Both the tantalum nitride layer and the tantalum layer serve as a barrier metal layer 125 L, for preventing diffusion of copper atoms from the corresponding copper layer 125 L 2 into the insulating interlayers 123 and 124 . Note that the same is true for the memory-side connection layer 125 M. [0051] In the semiconductor device of FIG. 1 , the formation of the common capacitor plate 120 is carried out by using the photolithography and etching process, the etching process and so on, but these processes are unrelated to the construction of the logic-circuit formation section 102 L. Namely, the processes do not contribute to the construction of the logic-circuit formation section 102 L. In this regard, the manufacture of the semiconductor device of FIG. 1 is inefficient. [0052] Also, in the semiconductor device of FIG. 1 , an aspect ratio of the logic-circuit-side contact structures 122 L is increased due to the existence of both the common capacitor plate 120 and the memory-side capacitor contact structure 122 M. Namely, the logic-circuit-side contact structures 122 L have an additional height corresponding to a thickness of both the common capacitor plate 120 and the memory-side contact structure 122 M. When the logic-circuit-side contact structures 122 L have a high aspect ratio, a defect is liable to occur in the formation of the logic-circuit-side contact structures 122 L, resulting in reduction in a manufacturing yield of the semiconductor devices. Also, when the logic-circuit-side contact structures 122 L have a high aspect ratio, an operation speed may decline at the logic-circuit section 12 L. [0053] In the semiconductor device of FIG. 1 , the aspect ratio of the logic contact structures 122 L can be made smaller by lowering the height of the capacitors 115 . Nevertheless, this should not be adopted in that the capacitance of the capacitors 115 becomes smaller, and thus a time period for refreshing the DRAM is shortened, resulting in a large power consumption for driving the DRAM. First Embodiment [0054] With reference to FIGS. 2A to 2P which are partial cross-sectional views, a first embodiment of the method manufacturing a semiconductor device according to the present invention is explained below. [0055] First, as shown in FIG. 2A , a p-type silicon substrate 11 , which may be derived from a monocrystalline silicon wafer, is prepared. The silicon substrate 11 is sectioned into a logic-circuit formation section 12 L in which a plurality of logic circuits should be formed, and a memory formation section 12 M in which a plurality of DRAM cells should be formed. [0056] Then, a plurality of element-isolation layers 13 are formed in the silicon substrate 11 by using an STI process, so that a plurality of transistor formation areas are defined on the surface of the silicon substrate 11 . In the logic-circuit formation section 12 L, only one of the defined transistor formation areas is representatively indicated by reference 14 L, and, in the memory formation section 12 M, only three of the defined transistor formation areas are representatively indicated by reference 14 M 1 , 14 M 2 and 14 M 3 , respectively. [0057] Next, as shown in FIG. 2B , an n-channel type MOS transistor is formed as a logic transistor in the transistor formation area 14 L, and includes a gate structure 15 L formed on the transistor formation area 14 L, and a pair of source/drain regions 16 L formed in the transistor formation area 14 L. The gate structure 15 L includes a gate insulating layer 15 L 1 formed on the transistor formation area 14 L, and agate electrode 15 L 2 formed on the gate insulating layer 15 L 1 . [0058] On the other hand, three n-channel type MOS transistors are respectively formed as DRAM transistors in the transistor formation areas 14 M 1 , 14 M 2 and 14 M 3 , and each of the DRAM transistors includes a gate structure (not shown) formed on the corresponding transistor formation area 14 M 1 , 14 M 2 or 14 M 3 , and a pair of source/drain regions 16 M 1 , 16 M 2 or 16 M 3 formed in the corresponding transistor formation area 14 M 1 , 14 M 2 or 14 M 3 . Similar to the gate structure 15 L, the gate structure (not shown) includes a gate insulating layer on the corresponding transistor formation area 104 M 1 , 104 M 2 or 104 M 3 , and a gate electrode formed on the gate insulating layer. [0059] Note, in FIG. 2B , only one of the source/drain regions 16 M 1 , 16 M 2 or 16 M 3 in each pair is illustrated. [0060] The formation of the logic transistors in the logic-circuit formation section 12 L and the formation of the DRAM transistors in the memory formation section 12 M are simultaneously carried out by using a well-known variety of processes such as a photolithography process, an etching process, a CVD process, a sputtering process and so on. [0061] After the formation of the logic and DRAM transistors is completed, suitable silicide layers 17 L are formed as interconnect layers on the surface of the silicon substrate 11 at the logic-circuit formation section 12 L so as to be electrically connected to the source/drain regions 16 L, respectively. [0062] Simultaneously, suitable silicide layers 17 M 1 , 17 M 2 and 17 M 3 are formed as interconnect layers on the surface of the silicon substrate 11 at the memory formation section 12 M so as to be electrically connected to the source/drain regions 16 M 1 , 16 M 2 and 16 M 3 , respectively. [0063] Note that the formation of the silicide layers 17 L, 17 M 1 , 17 M 2 and 17 M 3 may be carried out by a so-called salicide process. [0064] Then, a silicon dioxide layer 18 is formed as an insulating interlayer on the surface of the silicon substrate 11 by using a CVD process, and a surface of the silicon dioxide layer or insulating interlayer 18 is flattened by using a CMP process, so that the gate structures 15 L and the silicide layers or interconnect layers 17 L, 17 M 1 , 17 M 2 and 17 M 3 are covered with the insulating interlayer 18 . [0065] Next, as shown in FIG. 2C , a hole 19 for forming a bit-line contact structure is perforated in the insulating interlayer 18 by using a photolithography and etching process, so that a part of the silicide layer or interconnect layer 17 M, is exposed with the hole 19 . Then, a titanium nitride layer 20 , is formed on the surface of the insulating interlayer 18 so that an inner wall surface of the hole 19 is traversed by the titanium nitride layer 20 L, and then a tungsten layer 202 is formed on the titanium nitride layer 20 , so that the hole 19 is filled with tungsten. Note that the formation of the titanium nitride layer 20 , and the formation of the tungsten layer 20 2 may be continuously carried out by using a CVD process or a sputtering process. [0066] Next, as shown in FIG. 2D , both the tungsten layer 20 2 and the titanium nitride layer 20 L (see: FIG. 2C ) are subjected to a CMP process in which the redundant materials of the tungsten and titanium nitride layers 20 2 and 20 1 are removed from the surface of the insulating interlayer 18 , so that a bit-line contact structure 20 is formed in the hole 19 (see: FIG. 2C ) so as to be electrically connected to the interconnect layer 17 M 1 . [0067] Namely, the bit-line contact structure 20 is made of a titanium nitride layer 20 1 ′ derived from the titanium nitride layer 20 1 (see: FIG. 2C ), and a tungsten plug 202 ′ derived from the tungsten layer 20 2 (see: FIG. 2C ). Although the tungsten plug 20 2 ′ itself exhibits an inferior adhesive property to the silicon dioxide layer or insulating interlayer 18 , the titanium nitride layer 20 1 ′ exhibits a superior adhesive property to both the insulating interlayer 18 and the tungsten plug 20 2 ′, and thus it possible to ensure a secure adhesion of the bit-line contact structure 20 itself to the insulating interlayer 18 . [0068] After the formation of the bit-line contact structure 20 is completed, a tungsten layer 22 1 and a titanium nitride layer 22 2 are formed in order on the insulating interlayer 18 by using a CVD process or a sputtering process. [0069] Next, as shown in FIG. 2E , both the tungsten layer 22 1 and the titanium nitride layer 22 2 (see: FIG. 2D ) are patterned by using a photolithography and etching process, so that connection layers or bit-line layers 21 are formed on the insulating interlayer 18 at the memory formation section 12 L, with one of the illustrated bit-line layers 21 being electrically connected to the bit-line contact structure 20 . Namely, each of the bit-line layers 21 includes a tungsten layer 21 1 ′ derived from the tungsten layer 22 1 , and a titanium nitride layer 21 2 ′ derived from the titanium nitride layer 22 2 . [0070] Next, as shown in FIG. 2F , a silicon dioxide layer 22 is formed as an insulating interlayer on the insulating interlayer 18 by using a CVD process so that the bit-line layers 21 are covered with the insulating interlayer 22 , and a surface of the silicon dioxide layer or insulating interlayer 22 is flattened by using a CMP process. Note that each of the bit-line layers 21 can be securely adhered to the insulating interlayer 22 due to the titanium nitride layer 21 2 ′. [0071] Then, logic-circuit-side contact structures 23 L are formed in both the insulating interlayers 18 and 22 at the logic-circuit formation section 12 L, and memory-side contact structures 23 M are formed in both the insulating interlayers 18 and 22 at the memory formation section 12 M. Both the formation of the logic-circuit-side contact structures 23 L and the formation of the memory-side contact structures 23 M may be carried out in a similar manner to that in the formation of the bit-line contact structure 20 in the insulating interlayer 18 . In short, each of the logic-circuit-side and memory-side contact structures 23 L and 23 M includes a titanium nitride layer 23 1 ′ formed on an inner wall surface of a hole perforated in both the insulating interlayers 18 and 22 , and a tungsten plug 23 2 ′ formed on the titanium nitride layer 23 1 ′ so that the hole is filled with tungsten. [0072] Note that the logic-circuit-side contact structures 23 L are electrically connected to the respective logic-circuit-side interconnect layers 17 L. Also, note that the memory-side contact structures 23 M are electrically connected to the respective capacitor interconnect layers 17 M 2 and 17 M 3 . [0073] Next, as shown in FIG. 2G , a silicon nitride layer 24 and a silicon dioxide layer 25 are formed in order as insulating interlayers on the insulating interlayer 22 by using a CVD process and a CMP process. Then, openings 26 for forming capacitors are defined in both the insulating interlayers 24 and 25 at the memory formation section 12 M by using a photolithography and etching process, so that upper faces of the memory-side contact structures 23 M are exposed with the openings 26 . [0074] Next, as shown in FIG. 2H , a titanium nitride layer 27 is formed on the insulating interlayer 25 by using a CVD process or a sputtering process, so that the inner wall surfaces of the openings 26 are traversed by the titanium nitride layer 27 , with the titanium nitride layer 27 being electrically connected to the memory-side contact structures 23 M. Then, a photoresist layer 28 is formed on the titanium nitride layer 27 so that the openings 26 are filled with the photoresist material. [0075] Next, as shown in FIG. 21 , the photoresist layer 28 (see: FIG. 2H ) is subjected to a photolithography process so that respective photoresist masks 28 M are formed in the openings 26 . [0076] In particular, in the photolithography process, the photoresist layer 28 is exposed with ultraviolet rays so that the ultraviolet rays are penetrated into the portions of the photoresist layer 28 , which are received in the respective openings 26 , at a depth “d” of somewhat more than 100 nm measured from the upper peripheral edges of the openings 26 . Then, the exposed photoresist layer 28 is developed, resulting in the formation of the photoresist masks 28 M in the respective openings 26 . [0077] Next, as shown in FIG. 2J , the titanium nitride layer 27 is etched back by using a dry etching process or anisotropic etching process, so that a titanium nitride layer 27 H is formed as a lower capacitor electrode in each of the openings 26 . Note, an upper peripheral edge of each of the lower capacitor electrodes 27 M is positioned at a level of approximately 100 nm measured from the upper peripheral opening edges of the openings 26 . After the formation of the lower capacitor electrodes 27 M is completed, the photoresist masks 28 M are removed from the openings 26 . [0078] Next, as shown in FIG. 2K , a dielectric layer 29 , which is composed of a high dielectric constant material such as tantalum oxide, is formed on the insulating interlayer 25 by using a CVD process so that the inner wall surfaces of the openings 26 are traversed by the dielectric layer or tantalum oxide layer 29 . Then, a titanium nitride layer 30 1 is formed on the tantalum oxide layer 29 , and a tungsten layer 30 2 is formed on the titanium nitride layer 30 1 so that the openings 26 are filled with tungsten. [0079] Next, as shown in FIG. 2L , the tungsten, titanium nitride and tantalum oxide layers 30 2 , 30 1 and 29 (see: FIG. 2K ) are subjected to a CMP process in which the redundant materials of the tungsten, titanium nitride and tantalum oxide layers 30 2 , 30 1 and 29 are removed from the surface of the insulating interlayer 25 , so that a tantalum oxide layer 29 M, a titanium nitride layer 30 M 1 and a tungsten layer 30 M 2 are formed in each of the openings 26 (see: FIG. 2K ). The tantalum oxide layer 29 M serves as a capacitor dielectric layer, and both the titanium nitride layer 30 M, and the tungsten layer 30 M 2 define an upper capacitor electrode 30 M. In short, in each of the openings 26 (see: FIG. 2K ), the lower capacitor electrode 27 M, the capacitor dielectric layer 29 M and the upper capacitor electrode 30 M form a capacitor 31 . [0080] Note that each of the capacitors 31 features that the upper face of the capacitor dielectric layer 29 H and the upper capacitor electrode 30 M are coplanar with the surface of the insulating interlayer 25 . [0081] Next, as shown in FIG. 2M , logic-circuit-side contact structures 32 L are formed in both the insulating interlayers 24 and 25 at the logic-circuit formation section 12 L in a similar manner to that in the formation of the bit-line contact structure 20 in the insulating interlayer 18 . In short, each of the logic-circuit-side contact structures 32 L includes a titanium nitride layer 32 1 ′ formed on an inner wall surface of a hole perforated in both the insulating interlayers 24 and 25 , and a tungsten plug 32 2 ′ formed on the titanium nitride layer 32 1 ′ so that the hole is filled with tungsten. [0082] Note that the formation of the logic-circuit-side contact structures 32 L is carried out so that the respective logic-circuit-side contact structures 32 L are electrically connected to the logic-circuit-side contact structures 23 L formed in both the insulating interlayers 18 and 22 . [0083] Next, as shown in FIG. 2N , a silicon nitride layer 33 and a silicon dioxide layer 34 are formed in order as insulating interlayers on the insulating interlayer 25 by using a CVD process and a CMP process. Then, trenches 35 L for forming signal-line layers and a trench 35 M for forming a common capacitor electrode layer are formed in both the insulating interlayers 33 and 34 by using a photolithography and etching process. [0084] Next, as shown in FIG. 20 , a titanium nitride layer 36 , is formed on the insulating interlayer 34 by using a CVD process or a sputtering process so that the inner wall surfaces of the trenches 35 L and 35 M are traversed by the titanium nitride layer 361 , Then, a tungsten layer 362 is formed on the titanium nitride layer 36 , so that the trenches 34 L and 34 M are filled with tungsten. [0085] Next, as shown in FIG. 2P , both the tungsten layer 36 2 and the titanium nitride layer 36 1 (see: FIG. 20 ) are subjected to a CMP process in which the redundant materials of the tungsten and titanium nitride layers 36 2 and 36 1 are removed from the surface of the insulating interlayer 34 , so that both a titanium nitride layer 36 L 1 and a tungsten layer 36 L 2 are left in each of the trenches 34 L (see: FIG. 20 ), and so that both a titanium nitride layer 36 M 1 and a tungsten layer 36 M 2 are left in the trench 34 M (see; FIG. 20 ), resulting in completion of production of the semiconductor device featuring the logic-circuit formation section 12 L and the memory formation section 12 M. [0086] Note, in each of the trenches 34 L (see: FIG. 20 ), both the titanium nitride layer 36 L 1 and the tungsten layer 36 L 2 define a signal-line layer 36 L electrically connected to the corresponding logic-circuit-side contact structures 32 L. Also, note, in the trench 34 M (see: FIG. 20 ), both the titanium nitride layer 36 M 1 and the tungsten layer 36 M 2 defines a common capacitor electrode layer 36 M electrically connected to the upper capacitor electrodes 30 M of the capacitors 31 . [0087] In the semiconductor device of FIG. 2P , in each of the signal-line layers 36 L, both a tantalum nitride layer and tantalum layer may be substituted for the titanium nitride layer 36 L 1 , and a copper layer may be substituted for the tungsten layers 36 L 2 . Both the tantalum nitride layer and the tantalum layer serve as a barrier metal layer 36 L 1 for preventing diffusion of copper atoms from the corresponding copper layer 36 L 2 into the insulating interlayers 33 and 34 . Note that the same is true for the common capacitor electrode layer 36 M. [0088] As shown in FIG. 3 which is a partial plan view showing the memory formation section 12 M of the semiconductor device of FIG. 2P , the common capacitor electrode layer 36 M has a lattice-like configuration, and the capacitors 31 are regularly arranged so that an electrical connection is established between the common capacitor electrode layer 36 M and the upper capacitor electrodes 30 M of the capacitors 31 . [0089] With the arrangement of the semiconductor device of FIG. 2P , since the common capacitor electrode layer 36 M is formed in both the insulating interlayers 33 and 34 in which the signal-line layers 36 L are formed, it is possible to make an aspect ratio of the logic-circuit-side contact structures 32 L considerably smaller in comparison with the logic-circuit-side contact structures 122 L of FIG. 1 . [0090] For example, in the semiconductor device of FIG. 1 , when the capacitors 112 have the height of 400 nm, the height of the common capacitor plate 120 is on the order of 100 nm, and the height of the capacitor contact structure 122 M is on the order of 200 nm. Thus, the logic-circuit-side contact structures 122 L may have the height of 700 nm. [0091] On the other hand, in the semiconductor device of FIG. 2P , the logic contact structures 32 L have substantially the same height as that of the capacitors 31 . Accordingly, when the capacitors 31 has the height of 400 nm, the height of the logic contact structures 32 L is also 400 nm. [0092] Also, since the formation of the common capacitor electrode layer 36 M and the formation of the signal-line layers 36 L can be simultaneously carried out by using the photolithography and etching process, the CVD process or sputtering process, the CMP process and so on, it is possible to more efficiently manufacture the semiconductor device in comparison with the prior art semiconductor device of FIG. 1 . Second Embodiment [0093] With reference to FIGS. 4A to 4G which are partial cross-sectional views, a second embodiment of the method for manufacturing a semiconductor device according to the present invention is explained below. [0094] In the second embodiment, the same steps as those of FIG. 2A to FIG. 2H are executed. [0095] As shown in FIG. 4A which corresponds to FIG. 2I , the photoresist layer 28 (see: FIG. 2H ) is subjected to a photolithography process so that respective photoresist masks 28 M′ are formed in the openings 26 , with the photoresist masks 28 M′ having a smaller thickness than that of the photoresist masks 28 M of FIG. 21 . [0096] In particular, in the photolithography process, the photoresist layer 28 (see: FIG. 2H ) is exposed with ultraviolet rays so that the ultraviolet rays are penetrated into the portions of the photoresist layer 28 , which are received in the respective openings 26 , at a somewhat deeper depth “D” than the depth “d” (see: FIG. 21 ). Then, the exposed photoresist layer 28 (see: FIG. 2H ) is developed, resulting in the formation of the photoresist masks 28 M′ in the respective openings 26 . [0097] Next, as shown in FIG. 4B which corresponds to FIG. 2J , the titanium nitride layer 27 is etched back by using a dry etching process or anisotropic etching process, so that a titanium nitride layer or lower capacitor electrode 27 M′ is formed in each of the openings 26 . After the formation of the lower capacitor electrodes 27 M′ is completed, the photoresist masks 28 M′ are removed from the openings 26 . [0098] Next, as shown in FIG. 4C which corresponds to FIG. 2K , a dielectric layer 29 ′, which is composed of a high dielectric constant material such as tantalum oxide, is formed on the insulating interlayer 25 by using a CVD process so that the inner wall surfaces of the openings 26 are traversed by the dielectric layer or tantalum oxide layer 29 ′. Then, a titanium nitride layer 30 1 ′ is formed on the tantalum oxide layer 29 ′, and a tungsten layer 30 2 ′ is formed on the titanium nitride layer 30 1 ′ so that the openings 26 are filled with tungsten. [0099] Next, as shown in FIG. 4D which corresponds to FIG. 2L , the tungsten, titanium nitride and tantalum oxide layer 30 2 ′, 30 1 ′ and 29 ′ (see: FIG. 4C ) are etched back so that the redundant materials of the tungsten, titanium nitride and tantalum oxide layer 30 2 ′, 30 1 ′ and 29 ′ are removed from the surface of the insulating interlayer 25 , and so that respective recesses 26 ′ are defined at the locations of the openings 26 (see: FIG. 4C ), resulting in formation of a tantalum oxide layer 29 M′, a titanium nitride layer 30 M 1 ′ and a tungsten layer 30 M 2 ′ in each of the openings 26 (see: FIG. 4C ). The tantalum oxide layer 29 M′ serves as a capacitor dielectric layer, and both the titanium nitride layer 30 M 1 ′ and the tungsten layer 30 M 2 ′ define an upper capacitor electrode 30 M′. In short, in each of the openings 26 (see: FIG. 2K ), the lower capacitor electrode 27 M′, the capacitor dielectric layer 29 M′ and the upper capacitor electrode 30 M′ form a capacitor 31 ′. [0100] Next, as shown in FIG. 4E , holes 37 are formed in both the insulating interlayers 24 and 25 at the logic-circuit formation section 12 L by using a photolithography and etching process, so that the upper faces of the logic-circuit-side contact structures 23 L are exposed with the holes 37 . [0101] Then, a titanium nitride layer 38 1 is formed on the insulating interlayer 25 so that inner wall surfaces of the recesses 26 ′ and inner wall surfaces of the holes 37 are traversed by the titanium nitride layer 38 1 , and then a tungsten layer 38 2 is formed on the titanium nitride layer 38 1 so that the recesses 26 ′ and the holes 37 are filled with tungsten. Note that the formation of the titanium nitride layer 38 1 and the formation of the tungsten layer 38 2 may be continuously carried out by using a CVD process or a sputtering process. [0102] Next, as shown in FIG. 4F , both the tungsten layer 38 2 and the titanium nitride layer 38 1 are subjected to a CMP process in which the redundant materials of the tungsten and titanium nitride layers 38 2 and 38 1 are removed from the surface of the insulating interlayer 25 , so that logic-circuit-side contact structures 38 L are defined in both the insulating interlayers 24 and 25 at the logic-circuit formation section 12 L, and so that capacitor conductive plugs 38 M are defined in the respective recesses 26 ′ (see: FIG. 4E ). Namely, each of the logic-circuit-side contact structures 38 L includes a titanium nitride layer 38 L 1 formed on the inner wall surface of the corresponding hole 37 , and a tungsten layer 38 L 2 formed on the titanium nitride layer 38 L 1 , and each of the capacitor conductive plugs 38 M includes a titanium nitride layer 38 M 1 formed on the inner wall surface of the corresponding recesses 26 ′ and a tungsten layer 38 M 2 formed on the titanium nitride layer 38 M 1 . [0103] Note that each of the capacitor conductive Chugs 38 M is defined as an uppermost portion of the corresponding upper capacitor electrode 30 M′ with which an upper face of the capacitor dielectric layer 29 M′ is covered. [0104] Next, as shown in FIG. 4G , a silicon nitride layer 39 and a silicon dioxide layer 40 are formed in order as insulating interlayers on the insulating interlayer 25 by using a CVD process and a CMP process. Then, signal-line layers 41 L are formed in both the insulating interlayers 39 and 40 at the logic-circuit formation section 12 L so as to be electrically connected to the respective logic-circuit-side contact structures 38 L, and a common capacitor electrode layer 41 M is formed in both the insulating interlayers 39 and 40 at the memory formation section 12 M so as to be electrically connected to the capacitor conductive plugs 38 M. [0105] The formation of the signal-line layers 41 L and the common capacitor electrode layer 41 M may be carried out in a similar manner to that in the formation of the signal-line layers 36 L and the common capacitor electrode layer 36 M in the aforesaid first embodiment (see: FIGS. 2N to 2P ). Namely, each of the signal-line layers 41 L includes a titanium nitride layer 41 L 1 formed on an inner wall surface of a trench formed in both the insulating interlayers 39 and 40 , and a tungsten layer 41 L 2 formed on the titanium nitride layer 41 L 1 . Also, the common capacitor electrode layer 41 M includes a titanium nitride layer 41 M 1 formed on an inner wall surface of a trench defined in both the insulating interlayers 39 and 40 , and a tungsten layer 41 M 2 formed on the titanium nitride layer 41 M 1 . [0106] In the semiconductor device of FIG. 4G , in each of the signal-line layers 41 L, both a tantalum nitride layer and a tantalum layer may be substituted for the titanium nitride layer 41 L 1 , and a copper layer may be substituted for the tungsten layers 41 L 2 . Both the tantalum nitride layer and the tantalum layer serves as a barrier metal layer 41 L 1 for preventing diffusion of copper atoms from the corresponding copper layer 41 L 2 into the insulating interlayers 39 and 40 . Note that the same is true for the common capacitor electrode layer 41 M. [0107] As shown in FIG. 5 which is a partial plan view showing the memory formation section 12 M of the semiconductor device of FIG. 4M , the common capacitor electrode layer 41 M has a lattice-like configuration, and the capacitors 31 ′ are regularly arranged so that an electrical connection is established between the common capacitor electrode layer 41 M and the capacitor conductive plugs 38 M of the capacitors 31 ′. [0108] In FIG. 2P of the above-mentioned first embodiment, when the tungsten, titanium nitride and tantalum oxide layers 30 2 , 30 1 and 29 are subjected to the CMP process to thereby form the tantalum oxide layer 29 M, the titanium nitride layer 30 M 1 and the tungsten layer 30 M 2 in each of the openings 26 (see: FIGS. 2K and 2L ), the polished upper face of the tantalum oxide layer or capacitor dielectric layer 29 M may be subjected to corrosion due to an aqueous abrasive slurry used in the CMP process. [0109] However, according to the second embodiment, the corrosion problem concerning the tantalum oxide layer or capacitor dielectric layer 29 M′ (see: FIG. 4D ) can be completely prevented because the upper faces of the capacitor dielectric layers 29 M′ are covered with and protected by the respective capacitor conductive plugs 38 M (see: FIG. 4F ). Note, the thickness of the capacitor conductive plugs 38 M may be on the order of 100 nm. Third Embodiment [0110] With reference to FIGS. 6A to 6I which are partial cross-sectional views, a third embodiment of the method for manufacturing a semiconductor device according to the present invention is explained below. [0111] In the third embodiment, the same steps as those of FIG. 2A to FIG. 2F are executed. [0112] As shown in FIG. 6A , a silicon nitride layer 42 and a silicon dioxide layer 43 are formed in order as insulating interlayers on the insulating interlayer 22 by using a CVD process and a CMP process. Then, signal-line layers 44 L are formed in both the insulating interlayers 42 and 43 at the logic-circuit formation section 12 L so as to be electrically connected to the respective logic contact structures 23 L. The formation of the signal-line layers 44 L may be carried out in a similar manner to that in the formation of the signal-line layers 36 L in the aforesaid first embodiment (see: FIGS. 2N to 2P ). Namely, each of the signal-line layers 44 L includes a titanium nitride layer 44 L 1 formed on an inner wall surface of a trench defined in both the insulating interlayers 42 and 43 , and a tungsten layer 44 L 2 formed on the titanium nitride layer 44 L 1 . [0113] In each of the signal-line layers 44 L, both a tantalum nitride layer and a tantalum layer may be substituted for the titanium nitride layer 44 L 1 , and a copper layer may be substituted for the tungsten layers 44 L 2 . Both the tantalum nitride layer and the tantalum layer serve as a barrier metal layer 44 L 1 for preventing diffusion of copper atoms from the corresponding copper layer 44 L 2 into the insulating interlayers 42 and 43 . [0114] Next, as shown in FIG. 6B , a silicon nitride layer 45 , a silicon dioxide layer 46 , a silicon nitride layer 47 and a silicon dioxide layer 48 are formed in order as insulating interlayers on the insulating interlayer 43 by using a CVD process and a CMP process. Then, openings 49 for forming capacitors are defined in the insulating interlayers 48 , 47 , 46 , 45 , 43 and 42 at the memory formation section 12 M by using a photolithography and etching process, so that upper faces of the capacitor contact structures 23 M are exposed with the openings 49 . [0115] Next, as shown in FIG. 6C , a titanium nitride layer 50 M, a tantalum oxide layer 51 M, a titanium nitride layer 52 M 1 and a tungsten layer 52 M 2 are formed in each of the openings 49 (see: FIG. 6B ) in a similar manner to that in the formation of the titanium nitride layer 27 M′, the tantalum oxide layer 29 M′, the titanium nitride layer 30 M 1 ′ and the tungsten layer 30 M 2 ′ in the above-mentioned second embodiment (see: FIGS. 4A to 4D ), with respective recesses 49 ′ are defined at the locations of the openings 49 . [0116] The titanium nitride layer 50 M serves as a lower capacitor electrode, the tantalum oxide layer 51 M serves as a capacitor dielectric layer, and both the titanium nitride layer 52 M 1 and the tungsten layer 52 M 2 define an upper capacitor electrode 52 M. In short, in each of the openings 49 (see: FIG. 6B ), the lower capacitor electrode 50 M, the capacitor dielectric layer 51 M and the upper capacitor electrode 52 M form a capacitor 53 . [0117] Next, as shown in FIG. 6D , a trench 54 for forming a signal-line layer is formed in both the insulating interlayers 47 and 48 at the logic-circuit formation section 12 L. Then, a via hole 55 for forming a via plug is perforated in both the insulating interlayers 45 and 46 so as to be in communication with the trench 54 , and a part of a predetermined signal-line layer 44 L is exposed with the via hole 54 . Note that the formation of the trench 54 and the perforation of the via holes 55 may be sequentially carried out by using a photolithography and etching process. [0118] Next, as shown in FIG. 6E , a titanium nitride layer 56 1 is formed on the insulating interlayer 48 so that inner wall surfaces of the recesses 49 ′ and inner wall surfaces of both the via hole 54 and the trench 55 are traversed by the titanium nitride layer 56 1 , and then a tungsten layer 56 2 is formed on the titanium nitride layer 56 1 so that the recesses 29 ′ and both the via hole 54 and the trench 55 are filled with tungsten. Note, the formation of the titanium nitride layer 56 1 and the formation of the tungsten layer 56 2 may be continuously carried out by using a CVD process or a sputtering process. [0119] Next, as shown in FIG. 6F , both the tungsten layer 56 2 and the titanium nitride layer 56 1 are subjected to a CMP process in which the redundant materials of the tungsten and titanium nitride layers 56 2 and 56 1 are removed from the surface of the insulating interlayer 48 , so that a signal-line layer 56 L is defined in the trench 55 (see: FIG. 6E ), and so that capacitor conductive plugs 56 M are defined in the respective recesses 49 ′ (see: FIG. 6E ). Namely, the signal-line layer 56 L includes a titanium nitride layer 56 L, formed on the inner wall surface of the trench 55 (see: FIG. 6E ), and a tungsten layer 56 L 2 formed on the titanium nitride layer 56 L 1 , and each of the capacitor conductive plugs 56 M includes a titanium nitride layer 56 M 1 formed on the inner wall surface of the corresponding recesses 49 ′ (see: FIG. 6E ), and a tungsten layer 56 M 2 formed on the titanium nitride layer 56 M 1 . [0120] Note that the signal-line layer 56 L is electrically connected to a predetermined signal-line layer 44 L through a via plug 56 V, which includes a titanium nitride layer 56 V 1 formed on the inner wall surface of the via hole 54 (see: FIG. 6 E), and a tungsten layer 56 V 2 formed on the titanium nitride layer 56 V 1 . [0121] Similar to the capacitor conductive plugs 38 H of FIG. 4F , each of the capacitor conductive plugs 56 M is defined as an uppermost Portion of the corresponding upper capacitor electrode 52 M with which an upper face of the capacitor dielectric layer 51 M is covered. [0122] In the signal-line layer 56 with the via plug 56 V, both a tantalum nitride layer and a tantalum layer may be substituted for the titanium nitride layers 56 L 1 and 56 V 1 , and a copper layer may be substituted for the tungsten layers 44 L 2 . Both the tantalum nitride layer and the tantalum layer serve as a barrier metal layer 56 L 1 / 56 V 1 for preventing diffusion of copper atoms from the corresponding copper layer 56 L 2 / 56 V 2 into the insulating interlayers 42 and 43 . In this case, of course, in each of the capacitor conductive plugs 56 M, both a tantalum nitride layer and a tantalum layer are substituted for the titanium nitride layer 56 M 1 , and a copper layer is substituted for the tungsten layer 56 M 2 . [0123] Next, as shown in FIG. 6G , a silicon nitride layer 57 , a silicon dioxide layer 58 , a silicon nitride layer 59 and a silicon dioxide layer 60 are formed in order as insulating interlayers on the insulating interlayer 47 by using a CVD process and a CMP process. [0124] Then, a trench 61 forming a signal-line layer is formed in both the insulating interlayers 59 and 60 at the logic-circuit formation section 12 L, and a trench 62 forming a common capacitor electrode layer is formed in both the insulating interlayers 59 and 60 at the memory formation section 12 M. Note that the formation of the trenches 61 and 62 may be simultaneously carried out by using a photolithography and etching process. [0125] Subsequently, a via hole 63 for forming a via plug is perforated in both the insulating interlayers 57 and 58 at the logic-circuit-formation section 12 L so as to be in communication with the trench 61 , and a part of the signal-line layer 56 L is exposed with the via hole 63 . Also, via holes 64 for forming via plugs are perforated in both the insulating interlayers 57 and 58 at the memory formation section 12 M so as to be in communication with the trench 62 , and parts of the respective capacitor conductive plugs 56 M are exposed with the via holes 64 . Note that the perforation of the via holes 63 and 64 may be simultaneously carried out by using a photolithography and etching process. [0126] Next, as shown in FIG. 6H , a titanium nitride layer 65 1 is formed on the insulating interlayer 60 so that inner wall surfaces of the via holes 61 and 63 and inner wall surfaces of trenches 62 and 64 are traversed by the titanium nitride layer 65 1 , and then a tungsten layer 65 2 is formed on the titanium nitride layer 65 1 so that the via holes 61 and 63 and the trenches 62 and 64 are filled with tungsten. Note, the formation of the titanium nitride layer 65 1 and the formation of the tungsten layer 652 may be continuously carried out by using a CVD process or a sputtering process. [0127] Next, as shown in FIG. 6I , both the tungsten layer 65 2 and the titanium nitride layer 65 1 are subjected to a CMP process in which the redundant materials of the tungsten and titanium nitride layers 65 2 and 65 1 are removed from the surface of the insulating interlayer 60 , so that a signal-line layer 65 L is defined in the trench 61 (see: FIG. 6H ), and so that a common capacitor electrode layer 65 H is defined in the trench 62 (see: FIG. 6H ). Namely, the signal-line layer 65 L includes a titanium nitride layer 65 L 1 formed on the inner wall surface of the trench 61 (see: FIG. 6H ), and a tungsten layer 65 L 2 formed on the titanium nitride layer 65 L 1 , and the common capacitor electrode layer 65 M includes a titanium nitride layer 65 M 1 formed on the inner wall surface of the trench 62 (see: FIG. 6H ), and a tungsten layer 65 M 2 formed on the titanium nitride layer 65 M 1 . [0128] Note that the signal-line layer 65 L is electrically connected to the signal-line layer 56 L through a via plug 65 LV, which includes a titanium nitride layer 65 LV 1 formed on the inner wall surface of the via hole 63 (see: FIG. 6H ), and a tungsten layer 65 LV 2 formed on the titanium nitride layer 65 LV 1 . Also, the common capacitor electrode layer 65 M is electrically connected to the capacitor conductive plugs 56 M through respective via plugs 65 MV, each of which includes a titanium nitride layer 65 MV 1 formed on the inner wall surface of the corresponding via hole 64 (see: FIG. 6H ), and a tungsten layer 65 MV 2 formed on the titanium nitride layer 65 MV 1 . [0129] In the semiconductor device of FIG. 6I , in the signal-line layer 65 L with the via plug 65 LV, both a tantalum nitride layer and a tantalum layer may be substituted for the titanium nitride layers 65 L 1 and 65 LV 1 , and a copper layer may be substituted for the tungsten layers 65 L 2 and 65 LV 2 . Both the tantalum nitride layer and the tantalum layer serve as a barrier metal layer 65 L 1 / 65 LV 1 for preventing diffusion of copper atoms from the copper layer 65 L 2 / 65 LV 2 into the insulating interlayers 59 and 60 . Note that the same is true for the common capacitor electrode layer 41 M with the via plugs 65 MV. [0130] As shown in FIG. 7 which is a partial plan view showing the memory formation section 12 M of the semiconductor device of FIG. 6I , the common capacitor electrode layer 65 M has a lattice-like configuration, and the capacitors 53 are regularly arranged so that the common capacitor electrode layer 65 M is electrically connected to the capacitor conductive plugs 56 M through the intermediary of the via plugs 65 MV. [0131] In the third embodiment, although the capacitors 53 is formed in the same manner as in the above-mentioned second embodiment, the capacitors 53 may be formed in the same manner as in the above-mentioned first embodiment (see: FIGS. 2G to 2L ). [0132] As well known, in general, when a metal layer having a large area is flattened by using a CMP process, a surface of the metal layer tends to be undulated. Namely, before the surface of the metal layer can be prevented from being undulated, the CMP process must be carefully carried out. For example, in the prior art semiconductor device of FIG. 1 , it is necessary to carefully polish by the tungsten layer 119 before the surface of the tungsten layer 119 can be flattened. [0133] On the other hand, in the above-mentioned first, second and third embodiments, it is possible to easily flatten the surface of the common capacitor electrode layer 36 M, 41 M or 65 M by using a CMP process due to the lattice-like configuration thereof. [0134] Finally, it will be understood by those skilled in the art that the foregoing description is of preferred embodiments of the device and the method, and that various changes and modifications may be made to the present invention without departing from the spirit and scope thereof.

Description

Topics

Download Full PDF Version (Non-Commercial Use)

Patent Citations (3)

    Publication numberPublication dateAssigneeTitle
    US-2003092235-A1May 15, 2003Kabushiki Kaisha ToshibaSemiconductor integrated circuit and method for manufacturing the same
    US-6395600-B1May 28, 2002Micron Technology, Inc.Method of forming a contact structure and a container capacitor structure
    US-6528366-B1March 04, 2003Taiwan Semiconductor Manufacturing CompanyFabrication methods of vertical metal-insulator-metal (MIM) capacitor for advanced embedded DRAM applications

NO-Patent Citations (0)

    Title

Cited By (15)

    Publication numberPublication dateAssigneeTitle
    CN-102074560-AMay 25, 2011瑞萨电子株式会社半导体器件
    DE-112011105831-B4October 20, 2016Intel CorporationVerfahren zur Herstellung von Kondensatoren mit zurückgesetzter Bodenelektrode
    EP-2388820-A3July 01, 2015Renesas Electronics CorporationIntegration of memory cells comprising capacitors with logic circuits comprising interconnects
    US-2010123199-A1May 20, 2010Nec Electronics CorporationSemiconductor device
    US-2011001216-A1January 06, 2011Nec Electronics CorporationSemiconductor device and manufacturing method thereof
    US-2011121375-A1May 26, 2011Renesas Electronics CorporationSemiconductor device
    US-2014002976-A1January 02, 2014Ruth A. Brain, Joseph M. SteigerwaldRecessed bottom-electrode capacitors and methods of assembling same
    US-2015187777-A1July 02, 2015Taiwan Semiconductor Manufacturing Company LimitedSemiconductor arrangement with capacitor and method of fabricating the same
    US-8258039-B2September 04, 2012Renesas Electronics CorporationSemiconductor device and manufacturing method thereof
    US-8390046-B2March 05, 2013Renesas Electronics CorporationSemiconductor device
    US-8471322-B2June 25, 2013Renesas Electronics CorporationSemiconductor device and manufacturing method thereof
    US-8624328-B2January 07, 2014Renesas Electronics CorporationSemiconductor device
    US-9741817-B2August 22, 2017Tower Semiconductor Ltd.Method for manufacturing a trench metal insulator metal capacitor
    US-9825040-B2November 21, 2017Taiwan Semiconductor Manufacturing Company LimitedSemiconductor arrangement with capacitor and method of fabricating the same
    WO-2013070221-A1May 16, 2013Intel CorporationCondensateurs d'électrode inférieure en retrait et leurs procédés d'assemblage